D3T09 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Workshop Registration -- Advance Program -- Committees

Scope

As technology scales, various new types of defects are presenting unique challenges to the test community. New test defect and data based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-90nm technology nodes and their impact on product quality and in-field reliability. Defect and data-driven testing (D3T) has been in practice for a number of years and often used for yield learning and analysis. It is now gaining attention more than ever in production test. D3T uses data to reduce defect levels, increase reliability, and to diagnose and solve yield problems. D3T can provide feedbacks on which tests to add/remove, or test subsets. It can also be utilized for improving quality of logic test patterns vs. outlier analysis tests. However, test data has not been easily accessible by smaller companies and researchers in academia.

The IEEE International Workshop on Defect and Data-Driven Testing (D3T 2009) is aimed at addressing the above issues. Paper presentations on topics related to the topics listed below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

Outlier Identification
Data-Driven Testing (DDT)
Test Data Analysis
Yield Learning and Analysis Using DDT
Adaptive Test
Data-Mining Methods for Test Data Processing
Low Voltage Testing
Elevated Voltage Testing and Stress Testing

Reliability and Yield
Nanometer Test Challenges
Defect Coverage & Metrics
Mixed Current/Voltage Testing
Economics of Defect Based Testing
Fault Localization & Diagnosis
Noise and Crosstalk Testing
Transition and Delay Fault Testing

Workshop Registration

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For online registration go to: https://www.badgeguys.com/reg/2009/itc/register.aspx

Advance Program

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Thursday -- Friday

November 05, 2009 (Thursday)

4:00 PM - 5:00 PM	OPENING SESSION
4:00 - 4:10	Opening Remarks M. Tehranipoor ( Univ. of Connecticut)
4:10 - 5:00	Thursday Keynote Magdy Abadir (Freescale)

5:10 PM - 6:30 PM	Session 1: Statistical Analysis and Yield Chair – Nisar Ahmed (Texas Instruments)
	Manufacturing Processes for End-to-End Yield Optimization Matthias Kamm (Cisco)
	Data Driven Zero Tolerance for Defects (Invited Talk) LeRoy Winemberg (Freescale)
	Rapid Yield Learning through Short Loop Electrical Fault Localization Jacob Orbon (Verigy)

7:00 PM - 9:00 PM WORKSHOP WELCOME RECEPTION

November 06, 2009 (Friday)

8:00 AM - 9:20 AM	Tutorial: Data Collection and the New and Expanded STDF Format Ajay Koche (Test Technology Consultant)

9:30 AM - 10:30 AM	Session 2: Defect Based Testing Chair – Kohei Miyase (KIT)
	On-Chip Power Supply Noise Measurements Ekarat Laohavaleeson and Chintan Patel (UMBC)
	Verification of Convolution Relation Between Sensitized Path’s Gate Transients, Power Grid Impulse Responses and Power Port Transients Reza M. Rad (UMBC), Jim Plusquellic (UNM), Chintan Patel (UMBC), Abhishek Singh (nVidia)
	A mechanism to address di/dt noise during delay test Amitava Majumdar, Nehal Patel, Ramamurthy Setty, Arani Sinha (AMD)

10:30 AM - 10:50 AM COFFEE BREAK

10:50 AM - 11:50 AM	Session 3: Signal Integrity and Power-Aware Test Chair - TBD
	Extended Abstract: Developing a Novel Quality Metric for Path-Delay Fault Pattern Evaluation Junxia Ma, Jeremy Lee and Mohammad Tehranipoor (UConn)
	Optimizing the Percentage of X-Bits to Reduce Switching Activity Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen and Seiji Kajihara (KIT)
	Realistic Low Cost Framework for Supply Noise Aware Delay Test Compaction Zhongwei Jiang, Zheng Wang, Jing Wang and D. M. H. Walker (Texas A&M)

11:50 AM - 1:00 PM LUNCH

1:00 PM - 2:00 PM	Session 4: Industry Practices Chair – Hank Walker (Texas A&M)
	Statistical Outlier Method Applications Amit Nahar, Kenneth Butler, John Carulli and Charles Weinberger (Texas Instruments)
	Invited talk Anne Gattiker (IBM)

2:00 PM - 2:20 PM BREAK

2:20 PM - 4:00 PM	Panel Discussion - Test and Diagnosis for Parametric Failures Organizers: Mohammad Tehranipoor (UConn) Al Crouch (Asset-Intertech)

Committees

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Organizing Committee

General Chair
Mohammad Tehranipoor, Univ. of Connecticut

Program Chair
Al Crouch, Asset-Intertech

Vice Program Chair
Jeff Roehr, Mediatek

Finance Chair
Sankaran M. Menon, Intel

Publicity Chair
Arani Sinha, AMD

Publication Chair
Nissar Ahmed, TI

Steering Committee

Sankaran Menon, Intel
Adit Singh, Auburn Univ.
Hank Walker, Texas A&M
Hans Manhaeve, Q-Start Test
Jim Plusquellic, U. New Mexico

Program Committee

Rob Aitken, ARM
Tom Bartenstein, Cadence
Nemat Bidokhti, Cisco
Ken Butler, TI
Krish Chakrabarty, Duke Univ.
Sreejit Chakravarty, LSI Logic
John Carulli, TI
Bruce Cory, Nvidia
Jennifer Dworak, Brown University
Patrick Girard, LIRRM
Sandeep Goel, LSI Logic
Rohit Kapur, Synopsys
Ajay Koche, Verigy
Mike Laisne, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Teresa McLaurin, ARM
Amit Nahar, TI
Suriyaprakash Natarajan, Intel
Jay Orbon, Verigy
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Mani Soma, UW
Claude Thibeault,Ecole Tech
Li C. Wang, UCSB
Xiaoqing Wen, Kyushu Institute of Tech.
LeRoy Winemberg, Freescale
Qiang Xu, CUHK

For more information, visit us on the web at: http://d3t.tttc-events.org/

The Defect and Data-Driven Testing (D3T 2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).